Why Your Supercapacitor Bank Sizing Assumes Ideal Load Profiles and Fails in the Field

You ran the numbers. The spreadsheet says your supercapacitor bank can handle a 50A pulse for 2 seconds with a 10-second recovery. But on the factory floor, the voltage sags to the undervoltage lockout in 1.2 seconds. The bank runs hot. The cycle life estimate of 500,000 cycles? You're seeing 50,000. This isn't bad luck—it's the gap between ideal load assumptions and real-world stress.

Most sizing guides assume constant current, perfect thermal dissipation, and a flat temperature curve. Reality is messier. Bursts come in clusters. Ambient temps hit 60°C. ESR doubles. That 'safe' bank becomes a ticking bomb. Let's walk through the math that got you here—and the fixes you need.

The Promise vs. The Pavement: Why Ideal Loads Lie

The spreadsheet trap

Every bank starts in a spreadsheet. You punch in 10 amps for 30 seconds, then 2 amps for 120 seconds—a neat repeating rectangle. The math works. The voltage curve looks textbook. You slap on a 20% safety margin and call it done. I have watched three startups burn through six-figure budgets this way. The pavement doesn't respect your spreadsheet. That neat rectangle? In the site, a crane grabs a 400-amp surge for 1.2 seconds because a motor controller hiccups. Your bank sees that, sags hard below the undervoltage lockout, and the whole system browns out. Not a simulation failure—a real one, with real heat.

The catch is how we teach sizing. Most textbooks and white papers assume constant-current pulses with fixed rest periods. That's a convenient lie. Supercapacitor banks live in the messy margins—solar smoothing, regenerative braking on forklifts, bursty IoT transmitters. Real loads breathe. They spike, they hold, they glitch. And the ESR—equivalent series resistance—heats up nonlinearly when the current waveform looks like a seismic reading, not a duty cycle.

Real pulse patterns vs. textbook duty cycles

I once watched a data-logger trace from a solar-powered weather station. The textbook said: "3 amps for 5 seconds every 60 seconds." The trace showed 1.2 amps for 12 seconds, then 6.2 amps for 0.8 seconds, then nothing for 45 seconds, then a 9-amp burst because a cloud passed. Wrong order. Not yet. That hurts. The bank was sized for the average—2.4 amp-hours—but the peak current density was 30% higher than the datasheet rating. Six months later, the terminal seals bulged. Thermal runaway is not a dramatic fireball in this world; it's slow electrolyte dry-out, capacitance drift, and a system that fails one year early. You can't spreadsheet your way out of physics.

'The primary failure always looks like a component defect. It's usually a sizing problem wearing a disguise.'

— floor engineer, after swapping the same bank model three times on one site

Manufacturers specify pulse current limits at 25°C with forced air. Most enclosures hit 50°C. That's a hidden derating multiplier nobody writes down. The ESR doubles at high temperature, which means I²R losses quadruple for the same pulse. We fixed this on one project by cutting the peak load with a pre-charge resistor—simple, cheap, and the bank survived three years past the original design life. But nobody tries that until the smoke test fails.

Most teams skip this: the load profile you model is always wrong. Always. The question is how wrong and whether your bank can absorb the difference. Derating 20% is a placebo. You need to measure the actual current waveform on a prototype—or borrow data from a similar installation—then add headroom for the 2% of pulses that look nothing like the average. That's where the cost of failure lives: not in the routine cycles, but in the one spike that collapses the rail voltage.

What Ideal Load Profiles Assume That Reality Doesn't

Constant Power vs. Pulsed Power — the Shape of the Ask

The standard sizing spreadsheet assumes a neat, well-behaved current draw. A constant 10 A for thirty seconds, voltage falls in a straight line, capacitor bank delivers exactly what it promised. That sounds fine until you hook the bank to a real machine. Industrial actuators don't sip current — they gulp it. One millisecond at 80 A, then silence for 200 ms, then another gulp. The average current might be 12 A, but the peak current is an order of magnitude higher. Quick reality check: supercapacitor losses scale with current squared, not average. That 80 A pulse creates 64 times the internal heat of a steady 10 A draw. The datasheet curve for a 10 A discharge is irrelevant when your load looks like a spike train.

Most teams skip this: they take the peak power from the load specification and divide by the voltage range to get an average current for sizing. Wrong order. The voltage drop during a high-current pulse is dominated by the equivalent series resistance (ESR), not the capacitance. You can have three farads on the bus and still see the voltage collapse to the undervoltage lockout in the primary 5 milliseconds of a pulse — because the ESR drop stole 400 mV instantly. The capacitance was fine. The paper calculation was fine. The physical result was a bricked system.

Recovery phase Assumptions — the Silent Betrayal

The textbook model assumes the bank has infinite window to rest between discharges. The voltage rises back toward equilibrium as charge redistributes inside the cells. In the lab that takes maybe ten seconds. In the site the next pulse arrives in 300 ms. That hurts. I have seen a solar smoothing bank trip three times in one afternoon because the recovery interval kept shrinking as clouds rolled in — the capacitors never reached their nominal no-load voltage before the next surge hit. The sizing assumed a 15-second gap between events. Reality delivered an 8-second average with occasional 2-second clusters.

Partial recovery accumulates. Each pulse starts from a lower baseline voltage, so the same current pulse pulls the bank deeper into the brownout zone. The catch is that standard sizing formulas treat each cycle as an independent event, fully reset. They don't model the ratchet effect of sequential shallow discharges. A 20 % derating won't help here because the failure is temporal, not capacitive. You need to know the minimum inter-arrival window of your load pulses — not the average — and size for the worst-case burst sequence, not the steady-state duty cycle.

Temperature Independence of ESR and Capacitance — a Dangerous Fiction

Every supercapacitor datasheet prints a nominal ESR at 25 °C. That number is a lie by omission. At 0 °C the same cell can show ESR that's three times higher. At −20 °C it can be five times higher. The capacitance also drops — by 20 to 30 percent depending on the cell chemistry. Now run that 80 A pulse through a bank with tripled ESR. The internal voltage drop triples. The I²R heating spikes. And here is the editorial punch: the heat that builds up inside the cell from that opening high-ESR pulse raises the local temperature, which lowers the ESR for the next pulse — thermal runaway in reverse, but still destructive. You get a self-accelerating cycle of thermal stress that the steady-state 25 °C model never predicted.

One floor fix we used on a telecom backup bank was to oversize the capacitance by 60 % and add a passive pre-heat circuit for the coldest six months — not because the average load demanded it, but because the cold-weather ESR spike would have dropped the bus voltage below the modem's reset threshold on the initial deep discharge of the morning. The original sizing, done in a 22 °C office in July, assumed the bank would always behave like the datasheet said. It didn't.

'The load profile you test with is never the load profile that breaks your bank. The one you forgot to measure always is.'

— bench engineer, after a solar-powered irrigation controller failed twice in one growing season

What usually breaks primary is the gap between the assumed recovery phase and the real one, or between the datasheet ESR and the cold-morning ESR. Fix that by measuring your actual pulsed load shape — not the average, not the RMS, but the 5-millisecond peak-and-recovery envelope — and then add a thermal model for your operating temperature range. The spreadsheet won't do that for you. The simulator might, if you feed it the right pulse train. But the initial step is admitting that ideal load profiles are a convenient fiction, not an engineering foundation.

Inside the Bank: ESR, Capacitance Drift, and Thermal Runaway

How ESR Rises with Temperature and Frequency

Equivalent series resistance is never a flat number on the datasheet—it's a liar that shifts under load. You pick a cell rated at 2.5 mΩ at 25°C and 1 kHz, then slam it with a 10 kHz ripple current at 65°C ambient. That ESR? It climbs 35% before lunch. The physical mechanism is straightforward: electron scattering worsens as the electrolyte warms, and the porous carbon structure struggles to deliver charge at higher frequencies. Most teams skip this: they size the bank for DC resistance, then wonder why the voltage sag doubles under a real inverter's switching harmonics. I have watched a perfectly calculated 15-F bank drop to 11.2 F effective simply because the manufacturer's ESR curve was buried on page 14 of a 40-page document nobody read. The catch is that higher ESR means more I²R loss, which means more heat, which means even higher ESR. That hurts.

Capacitance Fade Under High RMS Current

Capacitance drift is not a slow aging effect—it can happen in one hot afternoon. Under sustained high RMS current, the electrode-electrolyte interface degrades locally. Think micro-cracking in the activated carbon matrix and blocked pore access from gas evolution. The datasheet promises 30% capacitance loss after 500,000 cycles under rated conditions. But your floor load is not rated conditions. It's 2.3× the rated RMS current with a 40% duty cycle burst every 90 seconds. At those levels, I have measured usable capacitance dropping 18% in 2,000 cycles—three days of operation. Wrong order. The bank fails the voltage hold-up spec long before the cycle life test would predict. Quick reality check: that 20% derating you applied? It covers manufacturing tolerance, not the dynamic loss from pore starvation under high-frequency pulsing.

'We sized for 5,000 cycles at 25°C, but the bank was dead by week two. The RMS was double the datasheet footnote we skipped.'

— site engineer, solar microgrid retrofit, late 2023

The Feedback Loop of Self-Heating

Thermal runaway in supercapacitors is quieter than in lithium—no flame, just a slow drift toward failure. The loop goes like this: ESR rise generates heat, heat accelerates electrolyte evaporation, evaporation increases ESR further, and the bank's internal temperature climbs 15°C above ambient inside a sealed enclosure. At that point, the capacitance drift accelerates nonlinearly. Most simulation tools assume uniform temperature across the bank. Not yet. The cells near the center of a 12-pack in a tightly packed enclosure run 8°C hotter than the outer cells. Those inner cells lose capacitance faster, forcing the outer cells to take more current, which unbalances the voltage distribution. The BMS or balancing circuit can't keep up because it was designed for slow equalization, not rapid divergence. I fixed one bank by spacing the cells 8 mm apart and adding a small fan—the capacitance retention jumped from 72% to 94% over a 10,000-cycle test. That said, the root cause was never the chemistry. It was the assumption that ESR and capacitance stay static. They don't. Not even close.

Worked Example: Sizing a Bank for Solar Smoothing

Assume 20% Cloud Transients vs. Actual 50% Swings

I sat down with a solar farm operator last year — their bank was dead inside eighteen months. The sizing sheet looked clean: assume a 20% irradiance dip for thirty seconds, size the supercapacitors to hold the DC bus at 750 V, job done. That sounds fine until a monsoon shelf cloud rolls in at 11:03 AM and the array output drops from 480 kW to 190 kW in under four seconds. The bank saw a 58% transient, not 20%. Bus voltage collapsed to 612 V. The inverter faulted. The bank didn't recover — not that day, not ever. Most teams treat cloud transients as a neat 0.2 per-unit step function. Reality delivers irregular, deep swings that last minutes, not seconds. The sizing math assumes a shallow dip you can ride out. The bench gives you a canyon.

Calculate Required Capacitance and ESR Budget

Let's run the numbers the right way — then watch them break. For a 100 kW smoothing application, a 20% transient at 750 V nominal requires roughly 106 farads to keep the voltage above 700 V for thirty seconds. Energy balance: ½·C·(V_initial² − V_final²) = P·t. Simple. Too simple. That calculation ignores the internal resistance heating that shifts your goalposts. A 58% transient demands 420 farads — four times the hardware. Most engineers derate the capacitance by 20% and call it conservative. They forget ESR. A typical 100‑F cell has maybe 0.3 mΩ ESR. Stack fifty cells and you get 15 mΩ. At 130 A discharge, that's a 1.95 V drop just from resistance — plus I²R heating that raises cell temperature 12 °C, which pushes ESR up another 8%. The budget you allocated for voltage sag vanishes into heat. I have seen banks designed for 10% voltage drop suffer 17% before the transient even ends.

‘We sized for 30 seconds of hold-up. The cloud stayed for four minutes. The bank stayed — as a smoking brick.’

— bench engineer, after a rooftop installation autopsy

Compare Ideal Lifespan vs. bench Degradation

The datasheet promises 500,000 cycles at 25 °C and rated voltage. That assumes a gentle 0.5 V ripple, not the 60 V swings you actually see. Every deep discharge eats into cycle life — not linearly, but exponentially. A bank that cycles between 750 V and 650 V loses roughly 40% of its expected life per 1000 events. After three years of real solar smoothing, I measured capacitance fade at 22% per cell. The bank that was supposed to last fifteen years needed replacement in year four. What usually breaks primary is the thermal runaway chain: deeper transients cause higher current; higher current raises ESR; higher ESR forces deeper voltage sag to meet power demand; deeper sag hardens the thermal load. One afternoon of 50% cloud coverage can age a bank more than a month of shallow cycling. The fix is not bigger margins — it's building the sizing model around the worst transient you can measure, not the worst you can imagine. Go log site irradiance for sixty days. That data will hurt. Use it anyway.

When the Math Breaks: Edge Cases That Kill Banks

Cold-start voltage dips

A supercapacitor bank that coasts through a 25°C bench test can collapse at −20°C. The physics is brutal: ESR climbs 2–4× as temperature drops, and your carefully calculated voltage floor vanishes. I once watched a solar-powered telemetry station fail before sunrise—three mornings in a row. The bank was sized for a 12V minimum, but at −15°C the internal resistance binge-dropped the terminal voltage to 9.8V under the initial real load. That hurts. The fix wasn't more capacitance; it was a pre-charge heater pad and a derating curve that respected cold-soak hours. Most teams skip this: they run a single warm-room test and declare victory. But floor data tells a different story—startup current in subzero conditions can punch below the nominal minimum in under 200 milliseconds.

Bursty regenerative braking in elevators

Elevator retrofits look perfect on paper. A supercap bank captures regen energy, shaves peak demand, and—if sized for the average 30-second cycle—seems bulletproof. Then the lunch rush hits. Three cars decelerate in quick succession, dumping energy back within 12 seconds. No recovery window. The bank soaks the first pulse, barely handles the second, and on the third the voltage balancing circuit can't react fast enough. Cell imbalance spikes, one module trips its overvoltage protection, and the whole string drops offline. Quick reality check—the elevator cab stops between floors. Not ideal. The culprit isn't total energy; it's rate. Regenerative bursts arrive faster than passive balancing can bleed excess charge. We fixed this by adding active balancers with 5× the bleed current and a pre-emptive discharge trigger that sheds energy into a resistor bank when the rate-of-rise exceeds 0.3 V/s. The alternative? Oversize the bank 40% and accept the cost penalty.

'The bank that works for a single elevator will fail for a bank of three elevators—same cycle, but no recovery gap.'

— floor note from a hotel retrofit in Chicago, where the gap between pulses dropped from 45 seconds to 11

Mixed chemistry banks and imbalance pitfalls

Hybrid banks—Li-ion cells paired with supercapacitors—sound elegant. The cap handles surges; the battery holds steady energy. But voltage balancing across two chemistries with different self-discharge rates is a nightmare. The supercaps leak 5–15% of their charge per day; the Li-ion cells lose maybe 2%. Over a weekend of idle slot, the capacitor string drifts downward while the battery string stays high. When the system reconnects, the imbalance triggers a protection cut. Worse: pulse currents that the cap bank handles gracefully will slam the Li-ion pack with ripple stress it was never designed for. I have seen a 48V hybrid bank show perfectly balanced voltages at noon and a 4V spread by Tuesday morning. The trade-off is brutal—active balancing that works for one chemistry often makes the other worse. Our solution was a diode-isolated DC-DC interface that decouples the chemistries entirely. It adds cost, but it stops the bank from killing itself during idle drift.

Edge cases like these are not rare anomalies. They're the seams where textbook math meets uncooperative physics. Ignore them, and your bank becomes a field failure statistic. Address them, and you earn the rare compliment: 'That bank just works.' Start by stress-testing your sizing at your actual low temperature, not the data-sheet minimum. Measure pulse recovery window, not just pulse duration. And never assume mixed chemistry banks will self-balance—they won't. Not without help.

Why Derating 20% Isn't Enough—and What to Do Instead

Derating myths — the 20% trap

Most teams I meet treat 20% derating like a sacred cow. Slap 20% headroom on voltage, knock 20% off rated current, and call it a day. That feels safe. It isn't. A supercapacitor bank sized for 2.7 V per cell, derated to 2.16 V, still dies inside six months when ambient hits 60 °C and the load pulses at 10 Hz. The derating number itself becomes a placebo — you feel protected while the electrolyte quietly dries out. Why? Because 20% on voltage says nothing about RMS current ripple, and it certainly doesn't account for the fact that your hold window requirement doubles in winter.

The real derating factors: temperature, RMS current, voltage hold window

You need three separate derating knobs, not one blanket percentage. Temperature first: a cell rated for 1,500 h at 65 °C drops to roughly 500 h at 75 °C — that's a 3× life penalty for every 10 °C rise. Derate voltage *and* current separately for your worst-case operating temperature, not the lab-spec 25 °C. RMS current is the silent killer. A bank that sees 5 A DC with a 20 A ripple at 1 kHz heats itself from the inside out — I once watched a 100 F pack lose 30% of its capacitance in 400 hours because nobody checked the ripple current against the datasheet's frequency-correction factor. Voltage hold window? That's the trap most miss. Your system demands 12 V for 10 seconds after input drops. At 25 °C, a 50 F bank works. At −10 °C, capacitance sags 20–30% — now 50 F becomes 35 F effective, and your hold phase collapses to 7 seconds. Wrong order.

Stress testing your bank before deployment

Here is what I do now, and it has saved three projects from field failure. Build a test jig that mimics your *worst* load cycle — not the average. Run it at the highest ambient temperature your enclosure will see (measure it, don't guess). Inject the maximum RMS current ripple your converter produces, and hold that for 24 hours while logging ESR and capacitance every 10 minutes. Then cold-soak the bank to −20 °C and repeat the voltage-hold test. If capacitance drops below your minimum hold-slot requirement at either extreme, you need a larger bank — not more derating. Most engineers skip this because it takes a day. A field recall takes months.

“We derated 20% on everything. The bank still failed after six months — electrolyte dry-out from internal heating we never modeled.”

— Field application engineer, solar smoothing project, after swapping to a 40% larger bank with separate thermal and ripple derating factors

One more thing: never trust a single derating factor from the datasheet. Manufacturers rate cells for ideal conditions — 25 °C, low ripple, no voltage-hold duty cycling. Your bank lives in a hot, vibrating cabinet with a choppy load. Pull the derating curves from the application notes, not the summary table. Then apply them sequentially: voltage derate by temperature, current derate by frequency, capacitance derate by temperature. Multiply those effects, don't average them. That will push you to a bank 30–50% larger than the 20% rule suggests. And that larger bank — that's the one that survives.

Reader FAQ: Common Sizing Mistakes and Fixes

Why does my bank overheat even though average power is low?

Because average power is a lie your thermal model tells itself. I have scrapped three banks that looked perfect on paper—average draw under 5 W, well within rated limits—yet the core hit 85 °C in under an hour. The culprit isn't the average; it's the peak-to-average ratio that ideal profiles smooth over. A solar smoothing bank might see a 200 ms current spike of 40 A when a cloud passes and the inverter demands immediate compensation. That burst dumps far more heat into the ESR than a steady 5 W draw ever could, and the thermal phase constant of a supercapacitor cell (typically 15–30 minutes) means heat piles up from one spike to the next. Most simulation tools plot RMS current—but RMS understates the heating effect when spikes are short and widely spaced. The fix? Model the distribution of instantaneous power, not the average. If your design spreadsheet only shows mean watts, expect smoke.

How do I account for unequal voltage sharing?

You don't "account for it" with a simple resistor divider and hope. That hurts. The typical 48 V string using six 16 V cells looks safe until you measure each terminal under load: one cell hits 2.85 V while another lags at 2.4 V, and the imbalance grows as capacitance drifts with temperature. Passive balancing resistors bleed only 10–20 mA—useless when load currents are 5 A or more. The trade-off is brutal: active balancers add cost and PCB space, but without them the overvoltage cell degrades faster, its ESR climbs, and you get thermal runaway in a single cell that drags the whole string down. I have watched a 10-cell bank lose 40 % of its usable energy inside 200 cycles because the balancing circuit was a afterthought. Don't assume your cells are identical—they never are. Measure leakage current per cell at assembly, bin them within 5 %, and use a balancing circuit that reacts faster than your load changes.

We sized for 10 A continuous and got 80 A transients. The bank lasted three months. The spreadsheet said five years.

— field technician, solar microgrid retrofit, 2023

Can I simulate real-world loads in SPICE?

Yes—but only if you feed it the right waveform. Most teams skip this: they plug a step load or a sine wave into LTSpice, get a clean voltage plot, and call it done. Real loads are ugly. A welding robot draws a 300 A pulse for 8 ms, then nothing for 2 seconds, then a 50 A tail that decays exponentially. SPICE can handle that if you build a piecewise linear source from oscilloscope captures—but the simulation time jumps from seconds to hours. The shortcut that fails is using a constant-power load model; supercaps react to current, not power, and the feedback loop between voltage droop and power demand creates oscillations your model never predicts. Better approach: take a 24-hour current trace from a data logger, downsample it to 1 kHz (most transients are captured at that rate), and run a transient analysis with a minimum timestep of 100 µs. Your laptop will groan. That groan is the sound of reality.

Practical Takeaways: Protect Your Next Bank

Three numbers to check: ESR, RMS current, max temperature

Stop guessing. Three metrics decide whether your bank survives or vents on the floor. Equivalent series resistance — ESR — is the first betrayer. That nice 0.5 mΩ printed on the datasheet? Measured at 25°C, usually with a fresh part. At 65°C ambient inside a sealed enclosure, ESR can climb 40% higher. I have watched a bank that looked perfect on paper hit 85°C junction temperature inside eighteen months — the ESR rose, losses multiplied, and the thermal runaway curve steepened fast. The RMS current rating is your second check. Many engineers grab the peak pulse current and assume the RMS will be low. Wrong order. Burst-mode loads with high duty cycles push RMS current above what the capacitor can sustain. Check the ripple current derating curve — not the headline number. Third: maximum operating temperature. Supercaps lose capacitance permanently above rated temp. A bank sized for 10,000 cycles at 25°C might deliver only 2,000 cycles at 55°C. That hurts.

Simulate with real load traces, not idealized pulses

Most teams skip this: they size the bank using a single worst-case pulse — say a 50-amp draw for three seconds. Then they file the design and move on. The catch is real loads cluster. A solar smoothing bank I audited last year faced eleven rapid charge-discharge cycles in four minutes because a cloud bank passed in broken patches. The idealized single-pulse simulation predicted 8°C rise. The actual thermal excursion hit 23°C. Why? The capacitor never recovered between bursts; heat accumulated. If you can't record your actual load profile for a week, use a high-resolution power logger — $200 buys enough data to catch these patterns. Simulate the trace against your bank model. You will find the weak spots. Quick reality check—does your software model include ESR drift with temperature? If not, the predicted voltage sag will be wrong by 15–30%. Simulate that drift too.

Build in 50% headroom for burst clusters

Twenty percent derating is the standard cop-out. It fails. For supercapacitor banks feeding intermittent high-power loads — think motor start-ups, grid frequency regulation, or pulse-forming networks — the load arrives in clusters. Three quick bursts, a pause, then five more. The bank sees cumulative heating the single-pulse model never accounts for. I now add 50% headroom on capacitance and RMS current for any application where burst clustering is possible. That means if your average demand needs 100 farads at 60 amps RMS, spec a 150-farad bank rated for 90 amps RMS. Yes, it costs more. Yes, it takes more space. But a bank that blows in month seven costs far more in downtime and field service. — We replaced four dead banks last quarter alone; all were sized using ideal profiles and zero burst margin.